1. Field of the Invention
The present invention relates to a memory cell array in which fin-FET memory cells of DRAM are arranged in the form of an array and which is advantageous for use as a memory device embedded in an LSI, a method of producing such a memory cell array, and a semiconductor device using such a memory cell array. More specifically, the present invention relates to a fin-FET memory cell array of DRAM, which can be disposed in a reduced area without causing a problem of multiple selection, a method of producing such a memory cell array, and a semiconductor circuit device using such a memory cell array.
2. Description of the Related Art
State-of-the-art high-density LSIs include a huge number of logic circuits and an embedded memory. In such an LSI, an embedded memory part occupies a large area relative to the total chip area. In order to further increase the integration density of LSIs to meet requirements for improved performance, it is needed to reduce the size of the embedded memory part. In view of the above, much effort has been made to reduce the size of SRAM which is advantageous in compatibility with logic circuits and the size of DRAM which is expected to be capable of being further reduced in size. However, SRAMs have a limit in reduction in size. On the other hand, DRAMs including memory cells each composed of one MOSFET and one capacitor need a complicated production process and is not good in compatibility with the production process of logic circuits. To solve the above problems, it has been proposed to configure a DRAM using memory cells each composed of one vertical double-gate transistor (hereinafter, such a DRAM will be referred to as a “1T-DRAM”) (see for example, Japanese Unexamined Patent Application Publication No. 2003-78026).
Logic circuits can also be produced using vertical double-gate transistors. In this case, 1T-DRAMs including memory cells each composed of vertical double-gate transistor have good compatibility with the production process of logic circuits. Compared with conventional DRAMs including memory cells each composed of one MOSFET and one capacitor, 1T-DRAMs including memory cells each composed of one vertical double-gate transistor are expected to be capable of being further reduced in size.
The vertical double-gate transistor refers to a MOSFET configured such that a 3-dimensional isolated region of silicon (Si) is formed on a supporting substrate and a MOSFET having two gate electrodes is formed in this 3-dimensional isolated region of silicon (Si) such that one gate electrode is formed on one side surface thereof and the other one is formed on the opposite side surface. In the vertical double-gate transistor having such a structure, because the channel of the MOSFET is controlled using the two gate electrodes, a reduction in a current flowing between the source and drain in a waiting state can be achieved. Thus, use of the vertical double-gate transistor structure makes it possible to solve problems caused by reduction in size of MOSFETs.
Referring to FIG. 1, a memory cell including a vertical double-gate transistor for use in a 1T-DRAM disclosed in Japanese Unexamined Patent Application Publication No. 2003-78026 is described below.
FIG. 1 shows one of memory cells used in the 1T-DRAM disclosed in Japanese Unexamined Patent Application Publication No. 2003-78026. In FIG. 1, reference numeral 1 denotes a semiconductor region (3-dimensional region of semiconductor), reference numeral 2 denotes a source electrode, reference numeral 3 denotes a gate electrode, reference numeral 4A denotes a first side-surface gate electrode, reference numeral 4B denotes a second side-surface gate electrode, and reference numeral 5 denotes drain electrodes. The source electrode 2 is formed on the top of the semiconductor region 1, and the drain electrodes 5 are formed in regions where the semiconductor region 1 is in contact with a semiconductor substrate, that is, in regions on the bottom of the semiconductor region 1.
When a charge is accumulated in one of the first side-surface gate electrode 4A and the second side-surface gate electrode 4B, the accumulated charge causes a change in the threshold voltage of the vertical double-gate transistor used in the 1T-DRAM. A logical value “0” may be assigned to this state in which the threshold voltage is shifted, and a logical value “1” may be assigned to the other state in which the threshold voltage has a normal value. Thus, it is possible to configure a DRAM in which states of respective cells are detected by detecting the change in threshold voltage.
To use a 1T-DRAM including memory cells composed of vertical double-gate transistors as an embedded memory in a practical LSI, it is needed that memory cells each composed of a vertical double-gate transistor be disposed in the form of an array, and interconnection lines be formed so as to adequately connect drain regions, source regions, first side-surface gate electrode, and second side-surface electrodes.
However, when memory cells each including a vertical double-gate transistor are disposed in the form of an array, the following problems can occur.
When drain regions, source regions, first side-surface gate electrodes, and second side-surface gate electrodes of vertical double-gate transistors in respective memory cells are connected by common interconnection lines extending in row and column directions, it is difficult to connect electrodes located at the bottom of 3-dimensional regions of semiconductor to common interconnection lines such as bit lines or word lines.
In the memory cell array structure, it is required that information written in each memory cell should be retained. If isolation regions are simply disposed between adjacent memory cells to electrically isolate drain regions, source regions, first side-surface electrodes, and second side-surface electrodes of respective memory cells, the result is an increase in the total area of the array, and it is difficult to realize a high-density memory cell array.
In the memory cell array structure, when a voltage is applied to a common interconnection line such as a bit line or a word line to select a particular one of memory cells, there is a possibility that a plurality of memory cells are selected because a plurality of memory cells are activated.
In view of the above, it is an object of the present invention to provide a memory cell array of 1T-DRAM having a high density and having no problem with multiple selection of memory cells, a method of producing such a memory cell array, and a semiconductor circuit device using such a memory cell array.